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solomon systech semiconductor technical data this document contains information on a new product. specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1702 rev 1.1 p 1/46 dec 2003 copyright ? 2003 solomon systech limited advance information 240 outputs common / segment driver SSD1702
solomon systech dec 2003 p 2/46 rev 1.1 SSD1702 table of contents 1. general description ............................................................................................................ .... 5 2. features ....................................................................................................................... ................. 5 3. ordering information ........................................................................................................... .. 5 4. block diagram .................................................................................................................. .......... 7 5. die pad coordinates ............................................................................................................ ..... 8 6. tab package pin assignment............................................................................................... 13 7. pin description................................................................................................................ .......... 19 8. functional block descriptions ........................................................................................ 22 9. functional operations ......................................................................................................... 2 4 10. display data and driver output pins mapping ............................................................ 26 11. precaution..................................................................................................................... ............. 27 12. maximum ratings................................................................................................................ ....... 28 13. dc characteristics............................................................................................................. .... 29 14. ac characteristics............................................................................................................. .... 31 15. application examples of common drivers ................................................................... 35 16. application examples of segment drivers .................................................................. 37 17. timing chart of cascade connection of segment drivers................................... 38 18. application examples ........................................................................................................... .39 19. tab package detail dimensions ......................................................................................... 40
SSD1702 rev 1.1 p 3/46 dec 2003 solomon systech table of tables table 1 - ordering information ................................................................................................. ................. 5 table 2 - SSD1702z die pad coordinates......................................................................................... ....... 10 table 3 - SSD1702t1 pin assignment ............................................................................................. ........ 14 table 4 - SSD1702t2 pin assignment ............................................................................................. ........ 16 table 5 - SSD1702t3 pin assignment ............................................................................................. ........ 18 table 6 - output level truth table for segment mode............................................................................ .24 table 7 - output level truth table for common mode ............................................................................ 2 5 table 8 - 4-bit parallel, segment mode......................................................................................... ........... 26 table 9 - 8-bit parallel, segment mode......................................................................................... ........... 26 table 10 - common mode......................................................................................................... ................ 26 table 11 - maximum ratings (voltage referenced to vss).................................................................. 28 table 12 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) ........................................................................... 29 table 13 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) ........................................................................... 30 table 14 - interface timing characteristics (unless otherwise specified, voltage referenced to vss, vdd = +3.0 to +3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) ................................................ 31 table 15 - interface timing characteristics (vdd ? vss = +2.4 to +3.0v, v0=+15.0 to +30.0v, t a = - 35 to 85 c)............................................................................................................................. ... 32 table 16 - interface timing characteristics (vdd - vss = +2.4 to +3.6v, v 0 =+15.0 to +30.0v, t a = -35 to 85 c)............................................................................................................................. ........ 34
solomon systech dec 2003 p 4/46 rev 1.1 SSD1702 table of figures figure 1 - block diagram of SSD1702............................................................................................ ........... 7 figure 2 - SSD1702z die pad assignment......................................................................................... ........ 8 figure 3 - alignment mark detail dimensions .................................................................................... ...... 9 figure 4 - SSD1702t1 pin assignment (copper view)........................................................................... 13 figure 5 - SSD1702t2 pin assignment (copper view)........................................................................... 15 figure 6 - SSD1702t3 pin assignment (copper view)........................................................................... 17 figure 7 - illustration of output voltages in segment mode ................................................................. 24 figure 8 - illustration of output voltages in common mode ................................................................. 25 figure 9 - recommended power up and down sequence .................................................................... 27 figure 10 - timing characteristics of SSD1702 in segment mode ...................................................... 33 figure 11 - timing characteristics of SSD1702 in common mode ...................................................... 34 figure 12 - application example of single mode (l/r = l) ................................................................... 35 figure 13 - application example of single mode (l/r = h) ................................................................... 35 figure 14 - application example of dual mode (l/r = l) ...................................................................... 36 figure 15 - application example of dual mode (l/r = h) ...................................................................... 36 figure 16 - application example of segment mode (l/r = l) ............................................................... 37 figure 17 - application example of segment mode (l/r = h) .............................................................. 37 figure 18 - timing chart of cascade connection of segment drivers .................................................. 38 figure 19 - typical configuration for 320x240 application ................................................................... 39 figure 20 - SSD1702t1 tab detail dimensions .................................................................................... .40 figure 21 - SSD1702t2 tab detail dimensions .................................................................................... .42 figure 22 - SSD1702t3 tab detail dimensions .................................................................................... .44
SSD1702 rev 1.1 p 5/46 dec 2003 solomon systech 1. general description SSD1702 is a 240-outputs lcd driver capable of both common or segment driving, selected by hardware pin setting. it is designed for high resolution dot matrix type lcd panel for the use on pda or terminal. SSD1702 can be used in cascade mode to support display system with more than 240 rows or columns. in segment mode, 4-bit or 8-bit parallel input modes are available through pin selection. 2. features both segment and common mode supply voltage for lc driver: +15.0 to +30.0 v supply voltage for logic system: +2.4 to +3.6 v 240 outputs for either common or segment driving pin selectable between common and segment mode low output impedance low power consumption segment mode maximum xck clock frequency: 20 mhz (vdd = +3.0 to +3.6v) 15 mhz (vdd = +2.4 to +3.0v) pin selectable 4-bit or 8-bit input modes automatic transfer function of enable signal automatically stop the internal clock after counting 240 bits of input data in chip select mode line latch circuit reset function when dispoff# active common mode maximum lp clock frequency: 1 mhz (vdd = +2.4 to 3.6v) built-in 240 bits bi-directional shift register single (240 bits shift register) or dual mode (two 120 bits shift register) operations shift register circuit reset function when dispoff# active 3. ordering information table 1 - ordering information ordering part number outerlead pitch (mm) package form reference remark SSD1702z n/a gold bump die figure 2 on page 7 - SSD1702t1r1 0.21 tab figure 20 on page 39 - SSD1702t2r1 0.20 tab figure 21 on page 41 - SSD1702t3r1 0.055 tab figure 22 on page 43 -
solomon systech dec 2003 p 6/46 rev 1.1 SSD1702
SSD1702 rev 1.1 p 7/46 dec 2003 solomon systech 4. block diagram figure 1 - block diagram of SSD1702 v 0 v 12 v 5 v 43 y240 y239.......................................................y2 y1 level shifter 240 bits level shifter 240 bits 4-level driver active control control logic data control 240 bits line latch / shift register data latch control v 5 v 43 v 12 v 0 fr dispoff# eio1 eio2 lp xck s/c md l/r 4bits*2 data latch 240 8 240 8 8 88 8 d0 d2 d1 d3 d5 d4 d7 d6 vdd vss ................................... power on reset ..............8 * 30............... data latch
solomon systech dec 2003 p 8/46 rev 1.1 SSD1702 5. die pad coordinates figure 2 - SSD1702z die pad assignment die size: 12.65mm x 1.25 mm die height: 533um bump size: pad 1, 102, 113, 358 65um x 50um pad 2-101 49um x 105um pad 103-112, 359-368 65um x 49um pad 114, 115, 356, 357 50um x 95um pad 116-355 33um x 95um alignm ent m ark: type size coordinate t shape 75um x 75um -5989.0, 147.3 + shape 75um x 75um 5989.0, 147.3 circle r-37.5um -5989.0,-215.0 circle r-37.5um 5989.0,-215.0 pad 1,2,3,?->102 gold bumps face up SSD1702z x y nc nc nc y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 . . . . . . . . . . . . . y231 y232 y233 y234 y235 y236 y237 y238 y239 y240 nc nc nc nc nc v43 (x5) v5 (x5) vss (x7) md md l/r l/r fr fr fr eio1 (x3) lp lp lp dispoff# dispoff# dispoff# xck xck xck d7 (x3) d6 (x3) d5 (x3) d4 (x3) d3 (x3) d2 (x3) d1 (x3) d0 (x3) eio2 (x3) s/c s/c vdd (x12) vss (x9) v5 (x5) v43 (x5) nc nc v0 (x5) v12 (x5) v0 (x5) v12 (x5) x y
SSD1702 rev 1.1 p 9/46 dec 2003 solomon systech t shape + shape circle unit in m figure 3 - alignment mark detail dimensions
solomon systech dec 2003 p 10/46 rev 1.1 SSD1702 table 2 - SSD1702z die pad coordinates pad no. pad name x y pad no. pad name x y pad no. pad name x y 1 nc -6181.5 -473.9 61 d7 1030.9 -473.9 121 y6 5640.0 495.9 2 nc -6102.7 -473.9 62 d7 1107.1 -473.9 122 y7 5592.0 495.9 3 v43 -6026.5 -473.9 63 d7 1183.3 -473.9 123 y8 5544.0 495.9 4 v43 -5950.3 -473.9 64 xck 1574.9 -473.9 124 y9 5496.0 495.9 5 v43 -5874.1 -473.9 65 xck 1651.1 -473.9 125 y10 5448.0 495.9 6 v43 -5797.9 -473.9 66 xck 1727.3 -473.9 126 y11 5400.0 495.9 7 v43 -5721.7 -473.9 67 dispoff# 1951.3 -473.9 127 y12 5352.0 495.9 8 v5 -5645.5 -473.9 68 dispoff# 2027.5 -473.9 128 y13 5304.0 495.9 9 v5 -5569.3 -473.9 69 dispoff# 2103.7 -473.9 129 y14 5256.0 495.9 10 v5 -5493.1 -473.9 70 lp 2495.3 -473.9 130 y15 5208.0 495.9 11 v5 -5416.9 -473.9 71 lp 2571.5 -473.9 131 y16 5160.0 495.9 12 v5 -5340.7 -473.9 72 lp 2647.7 -473.9 132 y17 5112.0 495.9 13 vss -5177.3 -473.9 73 eio1 2871.7 -473.9 133 y18 5064.0 495.9 14 vss -5101.1 -473.9 74 eio1 2947.9 -473.9 134 y19 5016.0 495.9 15 vss -5024.9 -473.9 75 eio1 3024.1 -473.9 135 y20 4968.0 495.9 16 vss -4948.7 -473.9 76 fr 3331.9 -473.9 136 y21 4920.0 495.9 17 vss -4872.5 -473.9 77 fr 3408.1 -473.9 137 y22 4872.0 495.9 18 vss -4796.3 -473.9 78 fr 3484.3 -473.9 138 y23 4824.0 495.9 19 vss -4720.1 -473.9 79 l/r 3875.9 -473.9 139 y24 4776.0 495.9 20 vss -4643.9 -473.9 80 l/r 3952.1 -473.9 140 y25 4728.0 495.9 21 vss -4567.7 -473.9 81 md 4176.1 -473.9 141 y26 4680.0 495.9 22 vdd -4259.9 -473.9 82 md 4252.3 -473.9 142 y27 4632.0 495.9 23 vdd -4183.7 -473.9 83 vss 4643.9 -473.9 143 y28 4584.0 495.9 24 vdd -4107.5 -473.9 84 vss 4720.1 -473.9 144 y29 4536.0 495.9 25 vdd -4031.3 -473.9 85 vss 4796.3 -473.9 145 y30 4488.0 495.9 26 vdd -3955.1 -473.9 86 vss 4872.5 -473.9 146 y31 4440.0 495.9 27 vdd -3878.9 -473.9 87 vss 4948.7 -473.9 147 y32 4392.0 495.9 28 vdd -3802.7 -473.9 88 vss 5024.9 -473.9 148 y33 4344.0 495.9 29 vdd -3726.5 -473.9 89 vss 5101.1 -473.9 149 y34 4296.0 495.9 30 vdd -3650.3 -473.9 90 vss 5177.3 -473.9 150 y35 4248.0 495.9 31 vdd -3574.1 -473.9 91 v5 5340.7 -473.9 151 y36 4200.0 495.9 32 vdd -3497.9 -473.9 92 v5 5416.9 -473.9 152 y37 4152.0 495.9 33 vdd -3421.7 -473.9 93 v5 5493.1 -473.9 153 y38 4104.0 495.9 34 vdd -3345.5 -473.9 94 v5 5569.3 -473.9 154 y39 4056.0 495.9 35 s/c -2950.9 -473.9 95 v5 5645.5 -473.9 155 y40 4008.0 495.9 36 s/c -2874.7 -473.9 96 v43 5721.7 -473.9 156 y41 3960.0 495.9 37 eio2 -2650.7 -473.9 97 v43 5797.9 -473.9 157 y42 3912.0 495.9 38 eio2 -2574.5 -473.9 98 v43 5874.1 -473.9 158 y43 3864.0 495.9 39 eio2 -2498.3 -473.9 99 v43 5950.3 -473.9 159 y44 3816.0 495.9 40 d0 -2106.7 -473.9 100 v43 6026.5 -473.9 160 y45 3768.0 495.9 41 d0 -2030.5 -473.9 101 nc 6102.7 -473.9 161 y46 3720.0 495.9 42 d0 -1954.3 -473.9 102 nc 6181.5 -473.9 162 y47 3672.0 495.9 43 d1 -1730.3 -473.9 103 v12 6181.5 -337.9 163 y48 3624.0 495.9 44 d1 -1654.1 -473.9 104 v12 6181.5 -261.7 164 y49 3576.0 495.9 45 d1 -1577.9 -473.9 105 v12 6181.5 -185.5 165 y50 3528.0 495.9 46 d2 -1186.3 -473.9 106 v12 6181.5 -109.3 166 y51 3480.0 495.9 47 d2 -1110.1 -473.9 107 v12 6181.5 -33.1 167 y52 3432.0 495.9 48 d2 -1033.9 -473.9 108 v0 6181.5 43.1 168 y53 3384.0 495.9 49 d3 -809.9 -473.9 109 v0 6181.5 119.3 169 y54 3336.0 495.9 50 d3 -733.7 -473.9 110 v0 6181.5 195.5 170 y55 3288.0 495.9 51 d3 -657.5 -473.9 111 v0 6181.5 271.7 171 y56 3240.0 495.9 52 d4 -265.9 -473.9 112 v0 6181.5 347.9 172 y57 3192.0 495.9 53 d4 -189.7 -473.9 113 nc 6181.5 495.9 173 y58 3144.0 495.9 54 d4 -113.5 -473.9 114 nc 6081.0 495.9 174 y59 3096.0 495.9 55 d5 110.5 -473.9 115 nc 5980.5 495.9 175 y60 3048.0 495.9 56 d5 186.7 -473.9 116 y1 5880.0 495.9 176 y61 3000.0 495.9 57 d5 262.9 -473.9 117 y2 5832.0 495.9 177 y62 2952.0 495.9 58 d6 654.5 -473.9 118 y3 5784.0 495.9 178 y63 2904.0 495.9 59 d6 730.7 -473.9 119 y4 5736.0 495.9 179 y64 2856.0 495.9 60 d6 806.9 -473.9 120 y5 5688.0 495.9 180 y65 2808.0 495.9
SSD1702 rev 1.1 p 11/46 dec 2003 solomon systech pad no. pad name x y pad no. pad name x y pad no. pad name x y 181 y66 2760.0 495.9 241 y126 -264.0 495.9 301 y186 -3288.0 495.9 182 y67 2712.0 495.9 242 y127 -312.0 495.9 302 y187 -3336.0 495.9 183 y68 2664.0 495.9 243 y128 -360.0 495.9 303 y188 -3384.0 495.9 184 y69 2616.0 495.9 244 y129 -408.0 495.9 304 y189 -3432.0 495.9 185 y70 2568.0 495.9 245 y130 -456.0 495.9 305 y190 -3480.0 495.9 186 y71 2520.0 495.9 246 y131 -504.0 495.9 306 y191 -3528.0 495.9 187 y72 2472.0 495.9 247 y132 -552.0 495.9 307 y192 -3576.0 495.9 188 y73 2424.0 495.9 248 y133 -600.0 495.9 308 y193 -3624.0 495.9 189 y74 2376.0 495.9 249 y134 -648.0 495.9 309 y194 -3672.0 495.9 190 y75 2328.0 495.9 250 y135 -696.0 495.9 310 y195 -3720.0 495.9 191 y76 2280.0 495.9 251 y136 -744.0 495.9 311 y196 -3768.0 495.9 192 y77 2232.0 495.9 252 y137 -792.0 495.9 312 y197 -3816.0 495.9 193 y78 2184.0 495.9 253 y138 -840.0 495.9 313 y198 -3864.0 495.9 194 y79 2136.0 495.9 254 y139 -888.0 495.9 314 y199 -3912.0 495.9 195 y80 2088.0 495.9 255 y140 -936.0 495.9 315 y200 -3960.0 495.9 196 y81 1896.0 495.9 256 y141 -984.0 495.9 316 y201 -4008.0 495.9 197 y82 1848.0 495.9 257 y142 -1032.0 495.9 317 y202 -4056.0 495.9 198 y83 1800.0 495.9 258 y143 -1080.0 495.9 318 y203 -4104.0 495.9 199 y84 1752.0 495.9 259 y144 -1128.0 495.9 319 y204 -4152.0 495.9 200 y85 1704.0 495.9 260 y145 -1176.0 495.9 320 y205 -4200.0 495.9 201 y86 1656.0 495.9 261 y146 -1224.0 495.9 321 y206 -4248.0 495.9 202 y87 1608.0 495.9 262 y147 -1272.0 495.9 322 y207 -4296.0 495.9 203 y88 1560.0 495.9 263 y148 -1320.0 495.9 323 y208 -4344.0 495.9 204 y89 1512.0 495.9 264 y149 -1368.0 495.9 324 y209 -4392.0 495.9 205 y90 1464.0 495.9 265 y150 -1416.0 495.9 325 y210 -4440.0 495.9 206 y91 1416.0 495.9 266 y151 -1464.0 495.9 326 y211 -4488.0 495.9 207 y92 1368.0 495.9 267 y152 -1512.0 495.9 327 y212 -4536.0 495.9 208 y93 1320.0 495.9 268 y153 -1560.0 495.9 328 y213 -4584.0 495.9 209 y94 1272.0 495.9 269 y154 -1608.0 495.9 329 y214 -4632.0 495.9 210 y95 1224.0 495.9 270 y155 -1656.0 495.9 330 y215 -4680.0 495.9 211 y96 1176.0 495.9 271 y156 -1704.0 495.9 331 y216 -4728.0 495.9 212 y97 1128.0 495.9 272 y157 -1752.0 495.9 332 y217 -4776.0 495.9 213 y98 1080.0 495.9 273 y158 -1800.0 495.9 333 y218 -4824.0 495.9 214 y99 1032.0 495.9 274 y159 -1848.0 495.9 334 y219 -4872.0 495.9 215 y100 984.0 495.9 275 y160 -1896.0 495.9 335 y220 -4920.0 495.9 216 y101 936.0 495.9 276 y161 -2088.0 495.9 336 y221 -4968.0 495.9 217 y102 888.0 495.9 277 y162 -2136.0 495.9 337 y222 -5016.0 495.9 218 y103 840.0 495.9 278 y163 -2184.0 495.9 338 y223 -5064.0 495.9 219 y104 792.0 495.9 279 y164 -2232.0 495.9 339 y224 -5112.0 495.9 220 y105 744.0 495.9 280 y165 -2280.0 495.9 340 y225 -5160.0 495.9 221 y106 696.0 495.9 281 y166 -2328.0 495.9 341 y226 -5208.0 495.9 222 y107 648.0 495.9 282 y167 -2376.0 495.9 342 y227 -5256.0 495.9 223 y108 600.0 495.9 283 y168 -2424.0 495.9 343 y228 -5304.0 495.9 224 y109 552.0 495.9 284 y169 -2472.0 495.9 344 y229 -5352.0 495.9 225 y110 504.0 495.9 285 y170 -2520.0 495.9 345 y230 -5400.0 495.9 226 y111 456.0 495.9 286 y171 -2568.0 495.9 346 y231 -5448.0 495.9 227 y112 408.0 495.9 287 y172 -2616.0 495.9 347 y232 -5496.0 495.9 228 y113 360.0 495.9 288 y173 -2664.0 495.9 348 y233 -5544.0 495.9 229 y114 312.0 495.9 289 y174 -2712.0 495.9 349 y234 -5592.0 495.9 230 y115 264.0 495.9 290 y175 -2760.0 495.9 350 y235 -5640.0 495.9 231 y116 216.0 495.9 291 y176 -2808.0 495.9 351 y236 -5688.0 495.9 232 y117 168.0 495.9 292 y177 -2856.0 495.9 352 y237 -5736.0 495.9 233 y118 120.0 495.9 293 y178 -2904.0 495.9 353 y238 -5784.0 495.9 234 y119 72.0 495.9 294 y179 -2952.0 495.9 354 y239 -5832.0 495.9 235 y120 24.0 495.9 295 y180 -3000.0 495.9 355 y240 -5880.0 495.9 236 y121 -24.0 495.9 296 y181 -3048.0 495.9 356 nc -5980.5 495.9 237 y122 -72.0 495.9 297 y182 -3096.0 495.9 357 nc -6081.0 495.9 238 y123 -120.0 495.9 298 y183 -3144.0 495.9 358 nc -6181.5 495.9 239 y124 -168.0 495.9 299 y184 -3192.0 495.9 359 v0 -6181.5 347.9 240 y125 -216.0 495.9 300 y185 -3240.0 495.9 360 v0 -6181.5 271.7
solomon systech dec 2003 p 12/46 rev 1.1 SSD1702 pad no. pad name x y 361 v0 -6181.5 195.5 362 v0 -6181.5 119.3 363 v0 -6181.5 43.1 364 v12 -6181.5 -33.1 365 v12 -6181.5 -109.3 366 v12 -6181.5 -185.5 367 v12 -6181.5 -261.7 368 v12 -6181.5 -337.9
SSD1702 rev 1.1 p 13/46 dec 2003 solomon systech 6. tab package pin assignment SSD1702t1 tab figure 4 - SSD1702t1 pin assignment (copper view)
solomon systech dec 2003 p 14/46 rev 1.1 SSD1702 table 3 - SSD1702t1 pin assignment pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 61 y26 121 y86 181 y146 241 y206 2 v0 62 y27 122 y87 182 y147 242 y207 3 v0 63 y28 123 y88 183 y148 243 y208 4 v12 64 y29 124 y89 184 y149 244 y209 5 v43 65 y30 125 y90 185 y150 245 y210 6 v5 66 y31 126 y91 186 y151 246 y211 7 nc 67 y32 127 y92 187 y152 247 y212 8 vdd 68 y33 128 y93 188 y153 248 y213 9 s/c 69 y34 129 y94 189 y154 249 y214 10 eio2 70 y35 130 y95 190 y155 250 y215 11 d0 71 y36 131 y96 191 y156 251 y216 12 d1 72 y37 132 y97 192 y157 252 y217 13 d2 73 y38 133 y98 193 y158 253 y218 14 d3 74 y39 134 y99 194 y159 254 y219 15 d4 75 y40 135 y100 195 y160 255 y220 16 d5 76 y41 136 y101 196 y161 256 y221 17 d6 77 y42 137 y102 197 y162 257 y222 18 d7 78 y43 138 y103 198 y163 258 y223 19 xck 79 y44 139 y104 199 y164 259 y224 20 dispoff# 80 y45 140 y105 200 y165 260 y225 21 lp 81 y46 141 y106 201 y166 261 y226 22 eio1 82 y47 142 y107 202 y167 262 y227 23 fr 83 y48 143 y108 203 y168 263 y228 24 l/r 84 y49 144 y109 204 y169 264 y229 25 md 85 y50 145 y110 205 y170 265 y230 26 nc 86 y51 146 y111 206 y171 266 y231 27 vss 87 y52 147 y112 207 y172 267 y232 28 nc 88 y53 148 y113 208 y173 268 y233 29 v5 89 y54 149 y114 209 y174 269 y234 30 v43 90 y55 150 y115 210 y175 270 y235 31 v12 91 y56 151 y116 211 y176 271 y236 32 v0 92 y57 152 y117 212 y177 272 y237 33 v0 93 y58 153 y118 213 y178 273 y238 34 nc 94 y59 154 y119 214 y179 274 y239 35 nc 95 y60 155 y120 215 y180 275 y240 36 y1 96 y61 156 y121 216 y181 276 nc 37 y2 97 y62 157 y122 217 y182 38 y3 98 y63 158 y123 218 y183 39 y4 99 y64 159 y124 219 y184 40 y5 100 y65 160 y125 220 y185 41 y6 101 y66 161 y126 221 y186 42 y7 102 y67 162 y127 222 y187 43 y8 103 y68 163 y128 223 y188 44 y9 104 y69 164 y129 224 y189 45 y10 105 y70 165 y130 225 y190 46 y11 106 y71 166 y131 226 y191 47 y12 107 y72 167 y132 227 y192 48 y13 108 y73 168 y133 228 y193 49 y14 109 y74 169 y134 229 y194
SSD1702 rev 1.1 p 15/46 dec 2003 solomon systech SSD1702t2 tab figure 5 - SSD1702t2 pin assignment (copper view)
solomon systech dec 2003 p 16/46 rev 1.1 SSD1702 table 4 - SSD1702t2 pin assignment pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 61 y28 121 y84 181 y144 241 nc 2 v0 62 y29 122 y85 182 y145 242 y201 3 v12 63 y30 123 y86 183 y146 243 y202 4 v43 64 y31 124 y87 184 y147 244 y203 5 v5 65 y32 125 y88 185 y148 245 y204 6 nc 66 y33 126 y89 186 y149 246 y205 7 vdd 67 y34 127 y90 187 y150 247 y206 8 s/c 68 y35 128 y91 188 y151 248 y207 9 eio2 69 y36 129 y92 189 y152 249 y208 10 d0 70 y37 130 y93 190 y153 250 y209 11 d1 71 y38 131 y94 191 y154 251 y210 12 d2 72 y39 132 y95 192 y155 252 y211 13 d3 73 y40 133 y96 193 y156 253 y212 14 d4 74 nc 134 y97 194 y157 254 y213 15 d5 75 nc 135 y98 195 y158 255 y214 16 d6 76 nc 136 y99 196 y159 256 y215 17 d7 77 nc 137 y100 197 y160 257 y216 18 xck 78 y41 138 y101 198 y161 258 y217 19 dispoff# 79 y42 139 y102 199 y162 259 y218 20 lp 80 y43 140 y103 200 y163 260 y219 21 eio1 81 y44 141 y104 201 y164 261 y220 22 fr 82 y45 142 y105 202 y165 262 y221 23 l/r 83 y46 143 y106 203 y166 263 y222 24 md 84 y47 144 y107 204 y167 264 y223 25 vss 85 y48 145 y108 205 y168 265 y224 26 v5 86 y49 146 y109 206 y169 266 y225 27 v43 87 y50 147 y110 207 y170 267 y226 28 v12 88 y51 148 y111 208 y171 268 y227 29 v0 89 y52 149 y112 209 y172 269 y228 30 nc 90 y53 150 y113 210 y173 270 y229 31 nc 91 y54 151 y114 211 y174 271 y230 32 nc 92 y55 152 y115 212 y175 272 y231 33 nc 93 y56 153 y116 213 y176 273 y232 34 y1 94 y57 154 y117 214 y177 274 y233 35 y2 95 y58 155 y118 215 y178 275 y234 36 y3 96 y59 156 y119 216 y179 276 y235 37 y4 97 y60 157 y120 217 y180 277 y236 38 y5 98 y61 158 y121 218 y181 278 y237 39 y6 99 y62 159 y122 219 y182 279 y238 40 y7 100 y63 160 y123 220 y183 280 y239 41 y8 101 y64 161 y124 221 y184 281 y240 42 y9 102 y65 162 y125 222 y185 282 nc 43 y10 103 y66 163 y126 223 y186 283 nc 44 y11 104 y67 164 y127 224 y187 284 nc 45 y12 105 y68 165 y128 225 y188 46 y13 106 y69 166 y129 226 y189 47 y14 107 y70 167 y130 227 y190 48 y15 108 y71 168 y131 228 y191 49 y16 109 y72 169 y132 229 y192
SSD1702 rev 1.1 p 17/46 dec 2003 solomon systech SSD1702t3 tab figure 6 - SSD1702t3 pin assignment (copper view)
solomon systech dec 2003 p 18/46 rev 1.1 SSD1702 table 5 - SSD1702t3 pin assignment pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 61 y28 121 y88 181 y148 241 y208 2 v0 62 y29 122 y89 182 y149 242 y209 3 v12 63 y30 123 y90 183 y150 243 y210 4 v43 64 y31 124 y91 184 y151 244 y211 5 v5 65 y32 125 y92 185 y152 245 y212 6 nc 66 y33 126 y93 186 y153 246 y213 7 vdd 67 y34 127 y94 187 y154 247 y214 8 s/c 68 y35 128 y95 188 y155 248 y215 9 eio2 69 y36 129 y96 189 y156 249 y216 10 d0 70 y37 130 y97 190 y157 250 y217 11 d1 71 y38 131 y98 191 y158 251 y218 12 d2 72 y39 132 y99 192 y159 252 y219 13 d3 73 y40 133 y100 193 y160 253 y220 14 d4 74 y41 134 y101 194 y161 254 y221 15 d5 75 y42 135 y102 195 y162 255 y222 16 d6 76 y43 136 y103 196 y163 256 y223 17 d7 77 y44 137 y104 197 y164 257 y224 18 xck 78 y45 138 y105 198 y165 258 y225 19 dispoff# 79 y46 139 y106 199 y166 259 y226 20 lp 80 y47 140 y107 200 y167 260 y227 21 eio1 81 y48 141 y108 201 y168 261 y228 22 fr 82 y49 142 y109 202 y169 262 y229 23 l/r 83 y50 143 y110 203 y170 263 y230 24 md 84 y51 144 y111 204 y171 264 y231 25 vss 85 y52 145 y112 205 y172 265 y232 26 v5 86 y53 146 y113 206 y173 266 y233 27 v43 87 y54 147 y114 207 y174 267 y234 28 v12 88 y55 148 y115 208 y175 268 y235 29 v0 89 y56 149 y116 209 y176 269 y236 30 nc 90 y57 150 y117 210 y177 270 y237 31 nc 91 y58 151 y118 211 y178 271 y238 32 nc 92 y59 152 y119 212 y179 272 y239 33 nc 93 y60 153 y120 213 y180 273 y240 34 y1 94 y61 154 y121 214 y181 274 nc 35 y2 95 y62 155 y122 215 y182 275 nc 36 y3 96 y63 156 y123 216 y183 276 nc 37 y4 97 y64 157 y124 217 y184 38 y5 98 y65 158 y125 218 y185 39 y6 99 y66 159 y126 219 y186 40 y7 100 y67 160 y127 220 y187 41 y8 101 y68 161 y128 221 y188 42 y9 102 y69 162 y129 222 y189 43 y10 103 y70 163 y130 223 y190 44 y11 104 y71 164 y131 224 y191 45 y12 105 y72 165 y132 225 y192 46 y13 106 y73 166 y133 226 y193 47 y14 107 y74 167 y134 227 y194 48 y15 108 y75 168 y135 228 y195 49 y16 109 y76 169 y136 229 y196
SSD1702 rev 1.1 p 19/46 dec 2003 solomon systech 6. pin description pin name segment mode common mode vdd this is the logic system power supply pin. vss ground pin v0, v12, v43, v5 these are the power supply pins for lc driving voltage. normally, the bias voltages used are set by a resistor divider. voltage level must be set such that vss v 5 v 43 v 12 v 0 . refer to section 8 for more details. s/c this pin switches the driver between segment and common mode. it should be set to h when segment mode is used. it should be set to l when common mode is used. md this is for the selection of input interface. when md is set to h, 4-bit parallel input mode is selected. when md is set to l, 8-bit parallel input mode is selected. the relationship between display data and driver output is shown in table 8 and table 9. this is for the selection between single mode and dual mode operation. when md is set to l, single mode operation is selected. when md is set to h, dual mode operation is selected. in single mode, the internal shift register will work as a 240-bit one. the scan pulse will run between y1 to y240. in dual mode, the internal shift register will be divided into two independent half, each with 120 bits. two independent scan pulses are allowed running simultaneously. one scan pulse run between y1 to y120 and the other run between y121 to y240. this makes the chip effectively work like two 120 channels common driver, which and thus allowing split screen application. application examples can be found in figure 12 to figure 15.
solomon systech dec 2003 p 20/46 rev 1.1 SSD1702 pin name segment mode common mode l/r l/r selects the scan direction of display data output. when l/r is set to l, data is read sequentially at the direction of y240 to y1. when l/r is set to h, data is read sequentially at the direction of y1 to y240. refer to table 8 and table 9 for more illustration. l/r selects shift direction of shift register. when l/r is set to l, data is shifted from y240 to y1. when l/r is set to h, data is shifted from y1 to y240. refer to table 10 for more illustration. dispoff# this is the display off control pin. when dispoff# is set to h, the input signal is level-shifted from logic voltage level to lcd driving voltage level and controls lcd drive circuit. when it is set to l, the contents stored in the line latch will be reset and y1-y240 will output v 5 level. however, data can still be read into data latch regardless of the condition of dispoff#. after the dispoff# function is cancelled, the driver will output deselected level (v 12 or v 43 , depends on the level of fr) until it encounters a falling edge of lp. dispoff# removal time must meet the ac characteristics shown in table 14 and table 15. otherwise, the driver may not be able to output the correct data. this is the display off control pin. when dispoff# is set to h, the input signal is level-shifted from logic voltage level to lcd driving voltage level and controls the lcd driving circuit. when it is set to l, the contents stored in the shift register will be reset and y1-y240 will output v 5 . after the dispoff# function is cancelled, the driver will output deselected level (v 12 or v 43 , depends on the level of fr) until it encounters a falling edge of lp. dispoff# removal time must meet the ac characteristics shown in table 16. otherwise, the driver may not be able to output the correct data. d0 ? d7 these are display data input pins. for 4 bits operation, only d0 - d3 are used and d4 - d7 should be connected to either vdd or vss. d0 - d6 are not used in common mode. they should be tied to vss. d7 is used as input pin in dual mode. data is input starting from the 121 st bit according to the data shift register. xck this is the shift clock input pin. data is read at the falling edge of the clock pulse. it is not used in common mode. it should be connected to vss or left open. lp this is the latch pulse input pin. data is latched at the falling edge of the clock pulse. this is the bi-directional shift register clock pulse input pin. data is shifted at the falling edge of this clock pulse.
SSD1702 rev 1.1 p 21/46 dec 2003 solomon systech pin name segment mode common mode fr fr is the ac signal input for lc driving waveform. normally it is the frame inversion signal. the input signal is level-shifted from logic voltage level to lc driving voltage level to control the lc driving circuit. the output voltage of the lc driver output pins are set by the line latch / shift register output signal and the fr signal. their relationship is shown in table 6 and table 7. eio1, eio2 these are the i/o pins for chip selection. when l/r is set to l, eio1 will be the output and eio2 will be the input. when l/r is set to h, eio1 will be the input and eio2 will be the output. after an lp signal is input and the eio(input) is set to l, the chip will be selected. it will be deselected automatically after reading 240 bits of data. eio(output) is normally h. it will only be pull l for one xck cycle (from falling edge to falling edge of xck) when 240 bits of data have been read. refer to figure 10 for details timing. these are the bi-directional shift register shift data i/o pin. when l/r is set to l, eio1 will be the output and eio2 will be the input. when l/r is set to h, eio1 will be the input and eio2 will be the output. a yd signal (vertical scanning start pulse) is expected at the eio(input). a h level at eio(input) during lp falling edge indicates the start of a vertical frame. refer to figure 11 for details timing. y1-y240 these are lc driver output pins. the output level can be referred table 6 and table 7. note: logic h means vdd level logic l means vss level
solomon systech dec 2003 p 22/46 rev 1.1 SSD1702 7. functional block descriptions active control in segment mode, this block controls the selection of the chip. following an lp signal input, and after the chip select signal is input, a select signal is generated internally until 240 bits of data have been read in. once the data input is completed, a selection signal for cascade connection will be output and the chip will be deselected. in common mode, this block controls the input/output data of bi-directional pins. data control when the chip is in segment mode with 4-bit parallel mode enable, this block collects one 4-bit data and transfers the data to data latch block in 4-bit format. when the chip is in segment mode with 8-bit parallel mode enable, this block collects one 8-bit data every xck cycle and transfers the data to data latch block in 8-bit format. this block has no function in common mode. data latch this block is only active in segment mode. it latches the data on the data bus which used to determine the output level of each output pins. the latched state of each lc driver output pin is controlled by the data latch control. data latch control this block is only active in segment mode. there are 30 data latch unit in the chip. each can store two 4-bit data. data latch control determines which of the data latch unit should receive the data from data control block. the shift direction is controlled by the control logic block. after reading every 4 or 8 bits of data (depending on 4-bit or 8-bit parallel mode), the selection signal will shift one bit to next data latch based on the state of the control circuit logic. line latch/shift register in segment mode, it simultaneously latches all 240 bits of data into data latch at the falling edge of the lp signal and output to the level shift block. in common mode, it shifts data from the data input pin by one bit at the falling edge of the lp signal. level shifter the logic voltage signal is level-shifted to the lcd driving voltage level and outputs to the driver block. 4-level driver this block is used to output appropriate lcd driving voltage level (v 0 , v 12 , v 43 , v 5 ) based on the combinations of s/c, fr and dispoff# signals and the data from the line latch or shift register.
SSD1702 rev 1.1 p 23/46 dec 2003 solomon systech control logic this block controls the operation of other blocks. in segment mode, when a lp pulse has been input, it controls the line latch to latches 240 bits data simultaneously and then resets the data latch control block. in common mode, this block controls the direction of data shift. power on reset reset all blocks during power on. all outputs (y1 ? y240) will be set to deselect level.
solomon systech dec 2003 p 24/46 rev 1.1 SSD1702 8. functional operations output voltage level mapping table 6 - output level truth table for segment mode fr latch data dispoff# driver output voltage level l l h v 43 l h h v 5 h l h v 12 h h h v 0 x x l v 5 figure 7 - illustration of output voltages in segment mode r r r r (n-4)r v 0 v 1 v 2 v 3 v 4 v 5 connect to v0 of segment driver connect to v12 of segment driver connect to v43 of segment driver connect to v5 of segment driver not use in segment driver not use in segment driver remark: ? in segment mode, the voltage levels v 1 and v 4 are not used. v 12 pin should be connected to voltage level v 2 and v 43 pin should be connected to voltage level v 3 . ? 1/n bias is assumed ? vss v 5 v 4 v 3 v 2 v 1 v 0 ? h: vdd; l: vss; x: don?t care. these pins should be tied to either h or l and avoided from floating. latch data h l h h l h x fr l l l h h h x dispoff# h h h h h h l
SSD1702 rev 1.1 p 25/46 dec 2003 solomon systech table 7 - output level truth table for common mode fr latch data dispoff# driver output voltage level l l h v 43 l h h v 0 h l h v 12 h h h v 5 x x l v 5 figure 8 - illustration of output voltages in common mode r r r r (n-4)r v 0 v 1 v 2 v 3 v 4 v 5 connect to v0 of common driver connect to v12 of common driver connect to v43 of common driver connect to v5 of common driver not use in common driver not use in common driver remark: ? in segment mode, the voltage levels v 2 and v 3 are not used. v 12 pin should be connected to voltage level v 1 and v 43 pin should be connected to voltage level v 4 . ? 1/n bias is assumed ? vss v 5 v 4 v 3 v 2 v 1 v 0 ? h: vdd; l: vss; x: don?t care. these pins should be tied to either h or l and avoided from floating. latch data l h l l h l x fr l l l h h h x dispoff# h h h h h h l
solomon systech dec 2003 p 26/46 rev 1.1 SSD1702 9. display data and driver output pins mapping table 8 ? 4-bit parallel, segment mode number of clock md l/r eio1 eio2 data input 1 st 2 nd 3 rd ? 58 th 59 th 60 th d0 y237 y233 y229 ? y9 y5 y1 d1 y238 y234 y230 ? y10 y6 y2 d2 y239 y235 y231 ? y11 y7 y3 h l output input d3 y240 y236 y232 ? y12 y8 y4 d0 y4 y8 y12 ? y232 y236 y240 d1 y3 y7 y11 ? y231 y235 y239 d2 y2 y6 y10 ? y230 y234 y238 h h input output d3 y1 y5 y9 ? y229 y233 y237 table 9 ? 8-bit parallel, segment mode number of clock md l/r eio1 eio2 data input 1 st 2 nd 3 rd ? 28 th 29 th 30 th d0 y233 y225 y217 ? y17 y9 y1 d1 y234 y226 y218 ? y18 y10 y2 d2 y235 y227 y219 ? y19 y11 y3 d3 y236 y228 y220 ? y20 y12 y4 d4 y237 y229 y221 ? y21 y13 y5 d5 y238 y230 y222 ? y22 y14 y6 d6 y239 y231 y223 ? y23 y15 y7 l l output input d7 y240 y232 y224 ? y24 y16 y8 d0 y8 y16 y24 ? y224 y232 y240 d1 y7 y15 y23 ? y223 y231 y239 d2 y6 y14 y22 ? y222 y230 y238 d3 y5 y13 y21 ? y221 y229 y237 d4 y4 y12 y20 ? y220 y228 y236 d5 y3 y11 y19 ? y219 y227 y235 d6 y2 y10 y18 ? y218 y226 y234 l h input output d7 y1 y9 y17 ? y217 y225 y233 table 10 ? common mode md l/r data transfer direction eio1 eio2 d7 l y240 y1 output input x l h y1 y240 input output x l y240 y121 y120 y1 output input input h h y1 y120 y121 y240 input output input where h: vdd l: vss x: don?t care. the pin should be tied to either h or l and avoided from floating.
SSD1702 rev 1.1 p 27/46 dec 2003 solomon systech 10. precaution this ic is a high voltage lc driver. if voltage is supplied to the lc driver power supply while the power supply of the logic system is floating, there may have high current flow inside the ic and permanently damaged the system. besides, the logic condition inside ic is undefined when the logic power is just applied, therefore a dispoff# signal is suggested for resetting the ic. the recommend power up and down sequence is as follow: power up: ? provide power to the logic system (vdd, vss) ? pull dispoff# to l ? provide the lcd driving power (v0, v12, v43, v5) ? dispoff# can then be pulled h for normal operation power down: ? pull dispoff# to l ? disconnect lcd driving power supply ? disconnect logic system power supply figure 9 ? recommended power up and down sequence vdd v 0 dispoff# vdd vss v0 vss vdd vss
solomon systech dec 2003 p 28/46 rev 1.1 SSD1702 11. maximum ratings table 11 - maximum ratings (voltage referenced to vss) symbol parameter value unit vdd logic supply voltage -0.3 to +4.0 v v 0 -0.3 to +32.0 v v 12 -0.3 to + v 0 +0.3 v v 43 -0.3 to + v 0 +0.3 v v 5 lc driving voltage supply -0.3 to + v 0 +0.3 v v i input voltage -0.3 to vdd+0.3 v t a operating temperature -30 to +85 c t stg storage temperature -65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics tables or pin description section. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range vss (v in or v out ) vdd. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either vss or vdd). unused outputs must be left open. all dummy and nc pins should be left open and unconnected. do not group dummy or nc pins together. this device may be light sensitive. caution should be taken to avoid exposed of this device to any light source during normal operation. this device is not radiation protected.
SSD1702 rev 1.1 p 29/46 dec 2003 solomon systech 12. dc characteristics segment mode table 12 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) symbol parameter test condition min typ max unit vdd vdd operation voltage - 2.4 - 3.6 v v0 v0 operation voltage - 15.0 - 30.0 v i stb stand-by current at vdd pin vdd = +3.6v, v 0 = +30v, v1 = vss, all input static - - 5 a i dd1 consumed current at vdd (chip is in deselected stage, i.e. non data-taking) vdd = +3.6v, v 0 = +30v, f xck = 20mhz, f lp = 333khz, f fr =1389hz, no-load, eio(input)=vdd, 4-bit mode, d0-d4 switch at every xck cycle - 450 900 a i dd2 consumed current at vdd (chip is in selected stage, i.e. data-taking) vdd = +3.6v, v 0 = +30v, f xck = 20mhz, f lp = 333khz, f fr =1389hz, no-load, eio(input)=vss, 4-bit mode, d0-d4 switch at every xck cycle - 750 1500 a i o consumed current at v0 vdd = +3.6v, v 0 = +30v, f xck = 20mhz, f lp = 333khz, f fr =1389hz, no-load, eio(input)=vss, 4-bit mode, d0-d4 switch at every xck cycle - - 2.5 ma v ih 0.8xvdd - - v v il input voltage at d0-d7, xck, lp, l/r, fr, md, s/c, eio1, eio2, dispoff# - - 0.2xvdd v v oh i oh = -0.4ma 0.9xvdd - - v v ol output voltage at eio1, eio2 i ol = +0.4ma - - 0.1xvdd v il ih v i = vdd - - 5 a il il input leakage current at d0-d7, xck, lp, l/r, fr, md, s/c, eio1, eio2, dispoff# v i = vss - - 5 a ?? v on ? = 0.5v, v 0 = +30v - 1.1 1.5 k ? r on output resistance ?? v on ? = 0.5v, v 0 = +20v - 1.1 2.0 k ?
solomon systech dec 2003 p 30/46 rev 1.1 SSD1702 common mode table 13 - dc characteristics (unless otherwise specified, voltage referenced to vss, vdd = 2.4 to 3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) symbol parameter test condition min typ max unit vdd vdd operation voltage - 2.4 - 3.6 v v0 v0 operation voltage - 15.0 - 30.0 v i stb stand-by current at vdd pin vdd = +3.6v, v 0 = +30v, v i = vss, all input static - - 5.0 a i dd1 consumed current at vdd pin vdd = +3.6v, v 0 = +30v, f lp = 333khz, f fr =1389hz, 1/240 duty operation, no-load - 15 100 a i o consumed current at v0 pin vdd = +3.6v, v0 = +30v, f lp = 333khz, f fr =1389hz, 1/240 duty operation, no-load - - 500 a v ih 0.8xvdd - - v v il input voltage at d0-d7, xck, lp, l/r, fr, md, s/c, eio1, eio2, dispoff# - - 0.2xvdd v v oh i oh = -0.4ma 0.9xvdd - - v v ol output voltage at eio1, eio2 i ol = +0.4ma - - 0.1xvdd v il ih v i = vdd - - 5 a il il input leakage current at d0-d7, xck, lp, l/r, fr, md, s/c, eio1, eio2, dispoff# v i = vss - - 5 a ?? v on ? = 0.5v, v 0 = +30v - 1.1 1.5 k ? r on output resistance at y1- y240 ?? v on ? = 0.5v, v 0 = +20v - 1.1 2.0 k ?
SSD1702 rev 1.1 p 31/46 dec 2003 solomon systech 13. ac characteristics segment mode table 14 - interface timing characteristics (unless otherwise specified, voltage referenced to vss, vdd = +3.0 to +3.6v, v 0 =+15.0 to +30.0v, t a = -30 to 85 c) symbol parameter test condition min typ max unit t wck shift clock period (1) t r , t f 10ns 50 - - ns t wckh shift clock h pulse width - 15 - - ns t wckl shift clock l pulse width - 15 - - ns t ds data setup time - 10 - - ns t dh data hold time - 12 - - ns t wlph latch pulse h pulse width - 15 - - ns t ld shift clock rise to latch pulse rise time - 0 - - ns t sl shift clock fall to latch pulse fall time - 25 - - ns t ls latch pulse rise to shift clock rise time - 25 - - ns t lh latch pulse fall to shift pulse fall time - 25 - - ns t r input signal rise time (2) - - - 50 ns t f input signal fall time (2) - - - 50 ns t s enable setup time - 10 - - ns t sd dispoff# removal time - 100 - - ns t wdl dispoff# l pulse width - 1.2 - - s t d output delay time1 cl = 15pf - - 30 ns t pd1 , t pd2 output delay time 2 cl = 15pf - 400 ns t pd3 output delay time 3 cl = 15pf - - 400 ns note: (1) take the cascade connection into consideration (2) (t ck -t wckh -t wckl )/2 is maximum in the case of high speed operation.
solomon systech dec 2003 p 32/46 rev 1.1 SSD1702 segment mode table 15 - interface timing characteristics (vdd ? vss = +2.4 to +3.0v, v0=+15.0 to +30.0v, t a = -35 to 85 c) symbol parameter test condition min typ max unit t wck shift clock period (1) t r , t f 10ns 66 - - ns t wckh shift clock h pulse width - 23 - - ns t wckl shift clock l pulse width - 23 - - ns t ds data setup time - 15 - - ns t dh data hold time - 23 - - ns t wlph latch pulse h pulse width - 30 - - ns t ld shift clock rise to latch pulse rise time - 0 - - ns t sl shift clock fall to latch pulse fall time - 50 - - ns t ls latch pulse rise to shift clock rise time - 30 - - ns t lh latch pulse fall to shift pulse fall time - 30 - - ns t r input signal rise time (2) - - - 50 ns t f input signal fall time (2) - - - 50 ns t s enable setup time - 15 - - ns t sd dispoff# removal time - 100 - - ns t wdl dispoff# l pulse width - 1.2 - - s t d output delay time1 cl = 15pf - - 41 ns t pd1 , t pd2 output delay time 2 cl = 15pf - - 400 s t pd3 output delay time 3 cl = 15pf - - 400 s note: (1) take the cascade connection into consideration (2) (t ck -t wckh -t wckl )/2 is maximum in the case of high speed operation.
SSD1702 rev 1.1 p 33/46 dec 2003 solomon systech figure 10 ? timing characteristics of SSD1702 in segment mode t pd1 t pd3 t wckh t lh 1 t ls t sl t d t s t wdl t f t r t ld lp xc k d0~d7 dispoff # t wlph first data of i th row last data of i-1 th row t wck t dh t wckl t sd t ds lp xc k eio (input) eio (output) f r lp dispoff# y1~y240 t pd2 in 4-bit mode, n = 240/4 = 60 in 8-bit mode, n = 240/8 = 30 2 n
solomon systech dec 2003 p 34/46 rev 1.1 SSD1702 common mode table 16 - interface timing characteristics (vdd - vss = +2.4 to +3.6v, v 0 =+15.0 to +30.0v, t a = -35 to 85 c) symbol parameter test condition min typ max unit t wlp shift clock period t r , t f 20ns 250 - - ns vdd = +3.0 to 3.6v 15 - - ns t wlph shift clock h pulse width vdd = +2.4 to 3.0v 30 - - ns t su data setup time - 30 - - ns t h data hold time - 50 - - ns t r input signal rise time - - - 50 ns t f input signal fall time - - - 50 ns t sd dispoff# removal time - 100 - - ns t wdl dispoff# l pulse width - 1.2 - - s t dl output delay time (1) c l =15 pf - - 200 ns t pd1 ,t pd2 output delay time (2) c l =15 pf - - 1.2 s t pd3 output delay time (3) c l =15 pf - - 1.2 s figure 11 ? timing characteristics of SSD1702 in common mode t h t su t pd3 t pd2 t pd1 t wdl t f t r lp eio(input) / d7 t wlp t wlph t dl t sd y1~y240 lp f r dispoff# eio ( out p ut ) dispoff #
SSD1702 rev 1.1 p 35/46 dec 2003 solomon systech 14. application examples of common drivers figure 12 ? application example of single mode (l/r = l) vss (vdd) vss dispoff# lp vss fr first last eio2 eio1 dispoff# lp md fr d7 l/r y240 y1 eio2 eio1 dispoff# lp md fr d7 l/r y240 y1 eio2 eio1 dispoff# lp md fr d7 l/r y240 y1 yd figure 13 ? application example of single mode (l/r = h) vss (vdd) eio2 eio1 dispoff# lp md fr d7 l/r y1 y240 dispoff# vdd lp vss fr first last yd eio2 eio1 dispoff# lp md fr d7 l/r y1 y240 eio2 eio1 dispoff# lp md fr d7 l/r y1 y240
solomon systech dec 2003 p 36/46 rev 1.1 SSD1702 figure 14 ? application example of dual mode (l/r = l) vss lp vss fr first (group a) last (group b) eio2 eio1 dispoff# lp md fr d7 l/r y240 y1 eio2 eio1 dispoff# lp md fr d7 l/r y240 y121 y120 y1 eio2 eio1 dispoff# lp md fr d7 l/r y240 y1 yd a vdd first (group b) last (group a) yd b dispoff# vss(vdd) figure 15 ? application example of dual mode (l/r = h) eio1 eio2 dispoff# lp md fr d7 l/r y1 y240 eio1 eio2 dispoff# lp md fr d7 l/r y1 y120 y121 y240 vss (vdd) dispoff# vdd lp vss fr first (group a) last (group b) yd a vdd first (group b) last (group a) yd b eio1 eio2 dispoff# lp md fr d7 l/r y1 y240
SSD1702 rev 1.1 p 37/46 dec 2003 solomon systech 15. application examples of segment drivers figure 16 ? application example of segment mode (l/r = l) d0-d7 vss eio2 eio1 xck lp md fr d0-d7 l/r y240 y1 eio2 eio1 xck lp md fr d0-d7 l/r y240 y1 eio2 eio1 xck lp md fr d0-d7 l/r y240 y1 xck lp vss fr first data last data 8 vss figure 17 ? application example of segment mode (l/r = h) eio2 eio1 xck lp md fr d0-d7 l/r y1 y240 lp xck vdd d0-d7 fr vss 8 eio2 eio1 xck lp md fr d0-d7 l/r y1 y240 eio2 eio1 xck lp md fr d0-d7 l/r y1 y240 first data last data vss
solomon systech dec 2003 p 38/46 rev 1.1 SSD1702 16. timing chart of cascade connection of segment drivers figure 18 ? timing chart of cascade connection of segment drivers eio (device b output, cascade to device c input) 2 2 2 fr 1 n 1 n 1 n 2 1 n eio (device a input) d0~d7 xck lp eio (device a output, cascade to device b input) eio (device c output, cascade to device d ) first data device a device b device c device d h l in 4-bit mode, n = 240/4 = 60 in 8-bit mode, n = 240/8 = 30 last data 2 1 n
SSD1702 rev 1.1 p 39/46 dec 2003 solomon systech 17. application examples figure 19 ? typical configuration for 320x240 application eio1 m d s/c l/r d0-d7 eio2 fr lp dispoff# xck eio1 m d s/c l/r d0-d7 eio2 fr lp dispoff# xck 320x240 dot matrix lcd panel yd fr lp dispoff# xck d0- d7 lcd controller vee v 0 v 1 v 2 v 3 v 4 v 5 vss vdd r r r r (n- 4)r y1-y320 y 1 - y 2 4 0 com1 com2 . . . . . . com239 com240 seg1 seg2 . . . . . . seg319 seg320 v dd, v ss, v0, v1, v4, v5 vdd, vss, v0, v2, v3, v5 SSD1702 ssd1703 segment driver common driver remark: ? the circuit is in 1/n bias ? vss v 5 v 4 v 3 v 2 v 1 v 0 v ee ? vee is the maximum driving voltage allowed, which is equal to or above v 0 . ? for common driver o v 0 should be connected to pin v 0 o v 1 should be connected to pin v 12 o v 4 should be connected to pin v 43 o v 5 should be connected to pin v 5 ? for segment driver o v 0 should be connected to pin v 0 o v 2 should be connected to pin v 12 o v 3 should be connected to pin v 43 o v 5 should be connected to pin v 5
solomon systech dec 2003 p 40/46 rev 1.1 SSD1702 18. tab package detail dimensions SSD1702t1 tab figure 20 ? SSD1702t1 tab detail dimensions s o l o mo n s s d 1 7 0 2 t 1
SSD1702 rev 1.1 p 41/46 dec 2003 solomon systech
solomon systech dec 2003 p 42/46 rev 1.1 SSD1702 SSD1702t2 tab figure 21 ? SSD1702t2 tab detail dimensions s s d 1 7 0 2 t 2 s o l o m o n
SSD1702 rev 1.1 p 43/46 dec 2003 solomon systech
solomon systech dec 2003 p 44/46 rev 1.1 SSD1702 SSD1702t3 tab figure 22 ? SSD1702t3 tab detail dimensions
SSD1702 rev 1.1 p 45/46 dec 2003 solomon systech
solomon systech dec 2003 p 46/46 rev 1.1 SSD1702
SSD1702 rev 1.1 p 47/46 dec 2003 solomon systech solomon systech reserves the right to make changes without further notice to any products herein. solomon systech makes no warr anty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does solomon systech assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typica ls" must be validated for each customer application by customer's technical experts. solomon systech does not convey any license under its patent rights nor the rights of others. solomon systech products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the solom on systech product could create a situation where personal injury or death may occur. should buyer purchase or use solomon systech products for any suc h unintended or unauthorized application, buyer shall indemnify and hold solomon systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that solomon systech was negligent regard ing the design or manufacture of the part. http://www.solomon-systech.com

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